Frequency measurement circuit

ABSTRACT

A frequency measurement circuit comprises a plurality of frequency measurement units  10, 20 , K 0  each of which counts a reference clock Cb during a counting period having a predetermined number of waves of an input signal Cin, each of the frequency measurement units counts the reference clock, with shifted counting periods, respectively. Moreover, an adder  14  is provided to add the counted numbers of the plurality of the frequency measurement units. By shift the counting periods, even if the phase of the input signal agrees with the phase of the reference clock at the time counting starts and at the time counting ends on a certain frequency measurement unit, there is scarcely any possibility of agreement of the phases on other frequency measurement units. Therefore, by utilization of the added number of counts, frequency can be measured with high accuracy. In addition, by making the counting periods being shifted with overlaping each other, extension of the measurement time is not required any longer.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a frequency measurement circuit capableof measuring the frequency of an input signal, by counting the number ofwaves of the input signal for a specified period, and more particularlyto a frequency measurement circuit that can measure the frequency with ahigher accuracy than the conventional circuits. The frequencymeasurement circuit of the present invention is applicable to a timeconstant regulation circuit to be mounted in a semiconductor integratedcircuit device, etc.

TECHNICAL BACKGROUND

When a circuit having a time constant like an oscillator or a filter ismounted in a semiconductor integrated circuit, the time constant couldbe changed, by a process change or operation conditions of thesemiconductor integrated circuit. In order to keep the time constant(for instance, an oscillating frequency, or specific frequency) of thesecircuits in a specific range, a time constant regulation device has beenused.

In Japanese Patent Application No. H10-222198 entitled “FILTERCHARACTERISTICS REGULATION METHOD AND APPARATUS” filed Aug. 6, 1998 bythe present applicant, for instance, the time constant regulation devicehas been disclosed as a filter characteristic regulation device forregulating the characteristic frequency of a filter. Such a timeconstant regulation apparatus, for instance., enters a step signalcontaining a wide frequency band signal into a filter, to allow thefilter to output the output signal corresponding to the characteristicfrequency of the filter, and measures the frequency of the outputsignal, and supplies a control signal to the filter so that the obtainedfrequency can be a desired characteristic frequency. Generally,frequency is measured by counting the number of waves of a referenceclock of the output signal during a specified cycle.

The adjustment accuracy of such a time constant regulation device asdescribed above is significantly affected by an accuracy of a frequencymeasurement circuit, a component element of the device. As describedabove, in the case of entering a step signal to measure the frequency ofthe output signal, since the waveform of the output signal can decay ina short period of time, it is required to count the number of waves of areference clock in a short period of time. Further, the frequency of thereference clock cannot be set with excessive freedom, due to therequirement of other circuits.

FIG. 11 is a configuration drawing of the conventional frequencymeasurement circuit. And, FIG. 12 shows an operating waveform diagram ofthe circuit. The frequency measurement circuit shown in FIG. 11 is acircuit to measure the frequency of the input signal Cin, and measuresthe cycle of the input signal Cin, utilizing the reference clock Cbhaving a shorter cycle than the input signal Cin, and known frequency.The frequency measurement circuit includes a select signal generatorcircuit 1 which counts the predetermined number of pulses (or number ofwaves) of the input signal Cin, when the input signal Cin is entered,and generates a select signal SEL during the counting, a selectorcircuit 2 to allow the reference clock Cb to pass through while theselect signal SEL is an H level, and a reference clock wave numbermeasurement circuit 3 to count the number of pulses (or number of waves)of the supplied reference clock Cb. Also, to the select signal generatorcircuit 1 and the reference clock wave number measurement circuit 3,both of which have a wave number measuring function, a reset signal Rstis supplied.

As shown in FIG. 12, when the cycle of the input signal Cin to bemeasured is expressed by tm, and the cycle of the reference clock C6 isexpressed by tB, by counting the reference clock Cb during the period ofthe M cycle of the input signal Cin, the cycle of the input signal Cincan be measured, and further, the frequency fm of the input signal Cincan be obtained. As shown in the operating waveform diagram in FIG. 12,by the reset signal Rst having at an L level for the first time, theselect signal generator circuit 1 and the reference clock wave numbermeasurement circuit 3 is reset. And, during the M cycle of the inputsignal Cin corresponding to the time from t0 through tM, the selectsignal SEL is kept at the H level, and the reference clock Cb issupplied to the reference clock wave number measurement circuit 3. Thereference clock wave number measurement circuit 3 counts, for instance,the number of the rising edges of the reference clock Cb during thattime, and outputs the final counted value as the frequency measurementresult OUT.

Generally, there are few cases where the phase of the input signal Cinperfectly agrees with the phase of the reference clock Cb. Therefore, bycounting the rising edges (or the falling edges, or both of the risingand falling edges) of the reference clock Cb, during the period from therising edge (t0) of the input signal Cin to the Mth rising edge (tM),the reference clock wave number measurement circuit 3 can count thenumber of waves N of the reference clock Cb with satisfactory accuracy.The period of counting can be either from the rising or the falling edgeto the rising or falling edge.

However, when the edge of the input signal and the edge of the referenceclock determining the operating period of both of the wave numbermeasurement circuits 1 and 3 are agreed at the time when measurementstarts, or when measurement ends, an error can take place in themeasurement made by the reference clock wave number measurement circuit3. In other words, as shown in FIG. 12, at the time when wave numbercounting starts to and at the time when the wave number counting endstM, the phase of the input signal Cin may agree with the phase of thereference clock Cb. In such a worst case, a wave number measurementcircuit in the reference clock wave number measurement circuit 3 canerroneously count the rising edge of the reference clock Cb, at thetimes tO and tM. This possibility is caused by the following two cases,e.g. (1) in the case where the circuit dose not count the rising edge ofthe reference clock Cb both at the times tO and tM; and (2) in the casewhere the circuit counts the rising edge of the reference clock Cb bothat the times tO and tM. In the case of (1), the total number of countsis N−1, and in the case of (2), the total number of count is N+1. Here,when the rising edge of the reference clock is counted at either time oftO or tM, there is no problem, since the counted result is the same asthe normal counted number.

In normal cases, if the counted number of waves of the reference clockmeasured by the reference clock wave number measurement circuit 3 is Nto the measured wave number M of the input signal Cin, when thefrequency of the reference clock is fB, the frequency fm of the inputsignal can be

fm=(M/N)fB  (1)

On the other hand, when both of the phases agreed, if the counted numberof waves of the reference clock is N±1 to the measured wave number M ofthe input signal, the frequency fm of the input signal is

fm=(M/(N±1))fB  (2)

Accordingly, the measurement error is as the following equation.$\begin{matrix}{{\Delta \quad f} = {{{\frac{M}{N \pm 1}\quad f_{B}} - {\frac{M}{N}\quad f_{B}}} = {\frac{\mp M}{N\quad \left( {N \pm 1} \right)}\quad f_{B}}}} & (3)\end{matrix}$

In the conventional examples, in order to improve the accuracy in themeasured frequency, according to the equation (3), it can be consideredto increase the counted number of waves N by increasing the measuredwave number M, or, by increasing the frequency fB of the reference clockCb to be counted by the wave number measurement circuit 3. However, ifthe measured number of waves M is increased, the measurement timebecomes longer.

As described above, in the case of entering a step signal into a filter,and measuring the frequency of the output waveform outputted from thefilter, since the output signal can decay in a short period of time, themeasurement time is not preferable to be extended. Also, when thereference clock is heightened, the current consumption is increased, andmoreover, since the reference clock cannot be set optionally in manycases, for reasons of using a semiconductor integrated circuit,thoughtless higher setting for the reference clock cannot be made.

It is therefore an object of the present invention to provide afrequency measurement circuit that enables the accuracy in measuringfrequency to be improved, even when the measurement time is short.

Another object of the present invention is to provide a frequencymeasurement circuit that enables the accuracy in measuring frequency tobe improved, without the need to raise the frequency of the referenceclock.

SUMMARY OF THE INVENTION

To attain the above objects, an aspect of the present invention providesa frequency measurement circuit comprising a plurality of frequencymeasurement units each of which counts a reference clock during acounting period having a predetermined number of waves of an inputsignal, each of the frequency measurement units counts the referenceclock, with shifted counting periods, respectively. Moreover, an adderis provided to add the counted numbers of the plurality of the frequencymeasurement units. By shifting the counting periods, even if the phaseof the input signal agrees with the phase of the reference clock at thetime counting starts and at the time counting ends on a certainfrequency measurement unit, there is scarcely any possibility ofagreement of the phases on other frequency measurement units. Therefore,by utilization of the added number of counts, frequency can be measuredwith high accuracy. In addition, by making the counting periods beingshifted with overlapping each other, extension of the measurement timeis not required any longer.

To attain the above objects, a second aspect of the present inventionprovides a frequency measurement circuit for measuring a frequency of aninput signal, comprising:

a first frequency measurement unit for counting the reference clockduring a first counting period having a predetermined number of waves ofthe input signal;

a second frequency measurement unit for counting the reference clockduring a second counting period having the predetermined number of wavesof the input signal; and

an adder for adding the counted numbers of the first and the secondfrequency measurement units, wherein

the first and second counting periods shift and overlap each other.

As to the first and the second frequency measurement units, three ormore units may be employed, if necessary. In that case, it is preferablethat the individual counting periods are also shifted each other.

To attain the above objects, a third aspect of the present inventionprovides a frequency measurement circuit for measuring a frequency of aninput signal, comprising:

a frequency measurement unit for counting a reference clock during acounting period having a predetermined number of waves of the inputsignal, wherein the frequency measurement unit counts the referenceclock by assigning a lighter weight to the counts at a starting time andending time of the counting period, compared with the other times.

In the case of the third aspect of the present invention, frequencymeasurement with high accuracy can be made without providing a pluralityof frequency measurement units.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows the principle of an embodiment.

FIG. 2 shows the configuration of a frequency measurement circuitaccording to a first embodiment.

FIG. 3 is an operating waveform diagram of the frequency measurementcircuit according to the first embodiment.

FIG. 4 is an operating waveform diagram showing an example of the casewhere the ratio of the cycle of the input signal to the cycle of thereference clock is 7:3.

FIG. 5 is an operating waveform diagram showing an example of the casewhere the ratio of the cycle of the input signal to the cycle of thereference clock is 3:1.

FIG. 6 shows the configuration of a frequency measurement circuitaccording to a second embodiment.

FIG. 7 is an operating waveform diagram of the frequency measurementcircuit according to the second embodiment.

FIG. 8 shows the configuration of a weight assigning wave numbermeasurement circuit.

FIG. 9 shows the configuration of a filter characteristic adjustmentcircuit, an applied example of the frequency measurement circuit.

FIG. 10 is an operating waveform diagram of the filter characteristicadjustment circuit shown in FIG. 9.

FIG. 11 shows the configuration of a conventional frequency measurementcircuit.

FIG. 12 is an operating waveform diagram of the conventional frequencymeasurement circuit.

PREFERRED EMBODIMENTS OF THE INVENTION

Embodiments of the present invention will now be described withreference to the drawings. However, such embodiments are not intended torestrict the technical scope of the present invention.

FIG. 1 shows the principle of the embodiment. According to the principleshown in FIG. 1, the frequency measurement circuit has a plurality offrequency measurement units 10, 20, . . . and K0. Like the conventionalexample, the frequency measurement unit 10 enters an input signal Cininto a select signal generator circuit 11 having a wave numbermeasurement function, and generates a select signal SELL that causes aselector circuit 12 a pass through state during a specified wave number(=M). And, a reference clock wave number measurement circuit 13 countswave number of the reference clock Cb passing through the selectorcircuit 12. The other frequency measurement units have the sameconfiguration as this unit. However, the counting period of each of thefrequency measurement units is shifted and partially overlapped.Therefore, the time when counting starts and the time when counting endsof each unit are not identical.

Herein, if the measured wave number during the counting period is M, theselect signal generator circuit 11 synchronizes with the rising or thefalling edge of the input signal Cin, or synchronizes with the risingand falling edges of the input signal, and causes the select signal an Hlevel during the period where these edges number M are to be counted. Asthe result of this, the reference clock wave number measurement circuit13 counts the reference clock Cb during the period where the wave numberof the input signal being M. This wave number measurement circuit 13counts the rising or the falling edge of the reference clock Cb, or bothof the rising and the falling edges. In short, the selector signalgenerator circuit 11 operates as synchronizing with the period tm of theinput signal Cin, and the reference clock wave number measurementcircuit 13 operates as synchronizing with the period tB of the referenceclock Cb. In that case, the frequency fm to be measured by each of thefrequency measurement units 10, 20, and K0 is as expressed by

fm=(M/N)fB  (4),

where the frequency of the reference clock Cb is fB.

In this embodiment, configuration is made to include a plurality offrequency measurement units, and to shift the time when each measurementunit starts measuring, by one cycle tm (or a plurality of cycles) of theinput signal Cin. Wherein, in the case where the operating cycle of theselect signal generator circuit 11 and the operating cycle of thereference clock wave number measurement circuit 13 (tm, tB) are in theindivisible relation, the phase relation between the input signal Cin(frequency fm) at the first frequency measurement circuit 10 and thereference clock Cb (frequency fB), and the phase relation between theinput signal Cin (frequency fm) at the second frequency measurement unit20 and the reference clock Cb (frequency fB) are mutually staggered.Therefore, if the edge timing of the input signal Cin agreed with theedge timing of the reference clock Cb at the time when measurementstarts and at the time when measurement ends, at the first frequencymeasurement unit 10, these edge timings would fail to agree at thesecond frequency measurement unit 20.

Therefore, in the case when the phase relation between the input signalCin (frequency fm) and the reference clock Cb (frequency fB) is notidentical, on all of the plurality (=K) of the frequency measurementunits, even if the phases agreed at a certain unit, on the other K−1units, the phases do not agree. In short, at the K−1 units, erroneouscounting of the reference clock cannot take place. As shown in FIG. 1,the counted number of each unit is added together at a computing element14, and the frequency of the input signal is measured, depending on thetotal counted numbers. The error in the frequency measurement in theabove case is expressed as follows: $\begin{matrix}\begin{matrix}{{\Delta \quad f} = \quad {{\frac{KM}{{\left( {K - 1} \right)\quad N} + \left( {N \pm 1} \right)}\quad f_{B}} - {\frac{KM}{KN}\quad f_{B}}}} \\{= \quad {\frac{\mp {KM}}{{KN}\quad \left( {{KN} \pm 1} \right)}\quad f_{B}}} \\{= \quad {\frac{\mp M}{N\quad \left( {{KN} \pm 1} \right)}\quad f_{B}}}\end{matrix} & (5)\end{matrix}$

In other words, when the above expressions (3) and (5) are compared, itcan be understood that, in this embodiment, the error in the frequencymeasurement is reduced to (N+1)/(KN+1) times of the case of theconventional method.

FIG. 2 shows the configuration of the frequency measurement circuit in afirst embodiment. FIG. 3 shows the operating waveform of the circuit.This is an example, where the number of frequency measurement units isK=2, in FIG. 1 showing the principle. In addition, the number of wavesduring the counting period is M, and all of select signal generatorcircuits 11 and 21, and reference clock wave number measurement circuits13 and 23 are to operate, as synchronizing with the rising edge of theinput. In other words, a select signal will be kept on an H level duringthe period from the rising edge through the Mth rising edge of the inputsignal Cin. Also, the number of rising edges of the reference clock Cbwill be counted as the number of waves.

As shown in FIG. 3, in this embodiment, the relation between the cycletm of the input signal Cin and the cycles, tB of the reference clock Cbis tm:tB=3.5:1. Therefore, the phase (rising edge, 0°) of the inputsignal Cin agrees with the phase of the reference clock Cb at the timest0, t2, t4, . . . (when even numbered waveforms) shown in FIG. 3.However, at the times t1, t3, t5 . . . (when odd numbered waveforms),the phase 10 of the input signal Cin does not agree with the phase ofthe reference clock Cb.

A first reset signal Rst1 will be given to the select signal generatorcircuit 11 and the reference clock wave number measurement circuit 13 ofa first frequency measurement unit 10. Also, the first reset signal Rst1may be further given to a reference clock wave number measurementcircuit 23 of a second frequency measurement circuit 20. In response tothe reset signal Rst1, the select signal generator circuit 11 counts theM rising edges from the rising edge (t0) of the next input signal Cin,and generates the select signal SEL1 on H level, during the time up totM. In response to the select signal SEL1, a select circuit 12 allowsthe reference clock Cb to pass through, and supplies the reference clockCb to the reference clock wave number measurement circuit 13.

In response to the first reset signal Rst1, the reference clock wavenumber measurement circuit 13, whose counted number is already reset,starts counting of the number of the rising edges (number of waves) ofthe reference clock Cb.

On the other hand, in response to the first reset signal Rst1, theselect signal generator circuit 11 generates a second reset signal Rst2,as synchronizing with the next rising edge (t0) of the input signal Cin.In response to the second reset signal Rst2, the circuit counts the Mrising edges from the rising edge (t1) of the next input signal Cin, andgenerates a select signal SEL2 of H level, during the period up to thetime tM+1. In response to the select signal SEL2, a reference clock wavenumber measurement circuit 23 in a second frequency measurement unitcounts the rising edge of the reference clock Cb.

Then, the counted number of both of the unit 10 and the unit 20 areadded by an adder 14, and the added counted number is outputted as thefrequency measurement result OUT. By taking an inverse number afterdividing the counted number by 2M, the frequency of the input signal Cincan be found.

Now, at the first frequency measurement unit 10, the phase of the inputsignal Cin agrees with the phase of the reference clock Cb at thecounting start time t0 and the counting end time tM, and also thetimings of both of the rising edges agree. Therefore, counting error cantake place at the start point and the end point of the wave numbermeasurement of the reference clock. In short, during the M cycle of theinput signal, there are two cases when the counted number becomes N, orbecomes N±1.

On the contrary, at the second frequency measurement unit 20, thecounting period shifts from the counting period of the first unit by onecycle of the input signal. Therefore, if the input signal and the cycleor frequency of the reference clock are in the indivisible relation, therising edge of the input signal never agrees with the rising edge of thereference clock at the start point t1 and the end point tM+1 of thecounting period of the second unit 20. Therefore, at the secondfrequency measurement unit 20, there is no possibility of count error,and the counted number of the wave number of the reference clock duringthe M cycle of the input signal becomes N.

The total counted number added the counted number obtained by the firstand the second frequency measurement units is, as shown in FIG. 3,whichever number of 2N, 2N−1, or 2N+1. Therefore, because there is thecase when the counted number becomes a wrong counted number of 2N±1,against the correct counted number of 2N, frequency measurement error Δfbecomes As follows: $\begin{matrix}\begin{matrix}{{\Delta \quad f} = \quad {{\frac{2M}{N + \left( {N \pm 1} \right)}\quad f_{B}} - {\frac{2M}{2N}\quad f_{B}}}} \\{= \quad {\frac{{\mp 2}M}{2N\quad \left( {{2N} \pm 1} \right)}\quad f_{B}}} \\{= \quad {\frac{\mp M}{N\quad \left( {{2N} \pm 1} \right)}\quad f_{B}}}\end{matrix} & (6)\end{matrix}$

In short, it can be understood that frequency measurement error becomes(N+1)/(2N+1) times, compared with the conventional example.

In the above embodiment, as clearly understood from the expressions (5)and (6), by increasing of the number of frequency measurement units, Kgiven in the expression (5) can be increased, and frequency measurementerror can be made fewer. However, it is not preferable to simplyincrease the number of frequency measurement units, as such increase canonly result in the increased scale of the integrated circuit. So, thefollowing shows description of the minimum scale of a frequencymeasurement circuit that enables the minimum frequency measurement errorto be obtained.

FIG. 4 is an operating waveform diagram showing an example when thecycles of the input signal and the reference clock are in the ratios of7:3. In the case when the cycles of the input signal Cin and thereference clock Cb are in the ratios of tm:tB=7:3, as shown in FIG. 4,if the rising edges of both of the clocks agree at the time t0, at thetime t3 after 3 cycles of the input signal, the rising edges must agreeagain. And after the time t3, this relation of 3 cycles of the inputsignal will be simply repeated.

In such a case, by setting for the counting period, for example, T1 fromthe time t0 to t3, T2 from the time t1 to t4 delayed for one cycle, andT3 from the time t2, further delayed for one cycle, error can beminimized. In other words, even if counting error can take place at thecounting period T1, at the counting periods T2 and T3, there is nopossibility of counting error. And at the counting period T4 startingfrom the time t3, there is again a possibility of counting error.

Therefore, it can be understood from the value of K given in the aboveexpression (5), that measurement error will become smaller when threefrequency measurement units are set for the counting periods T1, T2 andT3, than when two frequency measurement units are set for the countingperiods T1 and T2. However, if a frequency measurement unit having thecounting period T4 is added, counting error can take place at two units,thereby resulting in the same measurement error as in the case of havingtwo frequency measurement units.

That is, in the case of tm:tB=7:3 in FIG. 4, by setting of at leastthree frequency measurement units, measurement error can be minimized.In other words, in the case of having frequency measurement units of 3Nunits (N denotes a positive integer), this minimum measurement error canbe kept. However, it is not preferable to increase the number offrequency measurement units to 6 units or 9 units, since such increasecan only lead up to the increase in the power consumption, as well asthe increase in the circuit scale.

Thus, the requirement for a minimum measurement error or a maximummeasurement accuracy is to set frequency measurement units by at leastthe quotient obtained when the lowest common multiple of tm and tB aredivided by tm, for the cycle tm of the input signal and the cycle tB ofthe reference clock. Or, even when the number of units is set by integertimes of the quotient obtained when the lowest common multiple of tm andtB are divided by tm, the minimum error can be maintained.

Therefore, it is preferable to set the quantity of frequency measurementunits that can embody the minimum error as described above, depending onthe cycles of the input signal and the reference clock applicable to thefrequency measurement circuit in this embodiment.

FIG. 5 is an operating waveform diagram showing an example where thecycles of the input signal and the reference clock are in the ratios of3:1. When the cycles of the input signal Cin and the reference clock Cbare in the ratios of tm:tB=3:1, since the cycles are in the divisiblerelation, as shown in FIG. 5, when the rising edges of both of theclocks agreed at the time t0, every rising edge of the input signal mustagree with the rising edge of the reference clock. Therefore, even ifthe counting period is changed from t0 to t1, and from t1 to t2, at anymeasurement unit, counting error can take place.

Therefore, in such an example as shown in FIG. 5, a select signal isgenerated by utilization of both of the rising edge and the falling edgeof the input signal Cin. In short, the select signal generator circuitin the first measurement unit generates a select signal with H levelduring a first counting period T1 from the time t0 to t1. Also, theselect signal generator circuit in the second measurement unit generatesa select signal with H level during a second counting period T2 from thetime t0.5 to t1.5. That is to say, by setting of the cycle of the inputsignal Cin at tm/2, the newly set cycle tm/2 and the cycle tB of thereference clock are not in the divisible relation, tm:tB=1.5:1,therefore, at the time t0.5, the rising edge of the reference clocknever agrees with the rising edge of the input signal.

As described above, when the input signal and the reference clock are inthe relation as shown in FIG. 5, by utilization of both of the inputsignal edges, the cycles of both of the clocks can be in the indivisiblerelation so that a frequency measurement circuit with a fewer erroraccuracy using a plurality of counting cycles can be embodied.

Additionally, in the case shown in FIG. 4, the reference clock wavenumber measurement circuits 13 and 23 are also able to count both of therising edge and the falling edge of the reference clock Cb. The reasonis, unlike the case shown in FIG. 3, that the falling edge of thereference clock does not agree with the rising edge of the input signalat the times t1 and t2. In the case when both of the edges of thereference clock are to be counted, the counting number can be doubled atthe same counting period, so as to make error smaller.

In the case of utilizing both of the edges of the input signal or thereference clock, the defined cycles tm, and tB can be replaced with asemi-cycles. Therefore, in the case shown in FIG. 5, from the relationbetween the semi-cycle tm of the input signal and the semi-cycle tB ofthe reference clock, the quantity of measurement units in the case ofbecoming the minimum accuracy can be specified.

FIG. 6 shows a configuration of the frequency measurement circuit in asecond embodiment. In the second embodiment, a plurality of frequencymeasurement units are not set for the circuit like the first embodiment,but the circuit has only a single frequency measurement unit. And,because the unit counts, as assigning a lighter weight to the countingat the time when the counting period starts and at the time when thecounting period ends, compared with the counting at the other times, thesame result can be substantially obtained as in the case when the wavenumber of the reference clock is to be counted at a plurality of shiftedcounting periods.

On the frequency measurement circuit shown in FIG. 6, and an inputsignal wave number measurement circuit 16 to be supplied with the inputsignal Cin and to measure the wave number of the input signal isprovided. The input signal wave number measurement circuit 16 counts thewave number of the input signal Cin, in response to the reset signalRst, and outputs its counted value as a wave number measurement resultsignal S16. A select signal generator 17 causes the select signal SEL anH level during the time from count 1 up to a specified count (forinstance, M+1), in response to the wave number measurement result signalS16. A select circuit 12 allows the reference clock Cb to pass throughwhile the select signal SEL remains on an H level, and supplies itsreference clock to a weight assigning wave number measurement circuit15.

The weight assigning wave number measurement circuit 15 counts the wavenumber of the reference clock, with the amount of weighting depending onthe wave number measurement result signal S16. The amount of weightingis set so that the amount of weighting at the time when counting startsand at the time when counting ends is smaller than the amount ofweighting at other times.

FIG. 7 shows an operating waveform of the frequency measurement circuitin the second embodiment. This is also an example where out of therising edges of the input signal Cin, the rising edges of the inputsignal agree with the rising edges of the reference clock Cb at thetimes t0, t1, t4, . . . And the counting period is the period from thetime t0 to M+1 cycles of the time tM+1.

As described above, the input signal wave number measurement circuit 16starts counting of the wave number of the input signal Cin, in responseto the reset signal Rst. Therefore, the count value S16 increases, suchas at the time t0, the count value S16 becomes “1”, at the time t1, thecount value S16 becomes “2”, and so on. As the selector signal SELbecomes an H level, the supply of the reference clock Cb to the weightassigning wave number measurement circuit 15 starts from the time t0.

The weight assigning wave number measurement circuit 15 changes theamount of weighting for counting, based on the wave number measurementresult signal (count value) S16. As shown in FIG. 7, the circuit countswith the amount of weighting 1 at the cycle of the time t0, and from thecycle of the time t1 to the cycle of the time tM, the circuit countswith the amount of weighting 2, and further, at the cycle of the timetM+1, the circuit counts with the amount of weighting 1 again. As theresult, the weight assigning wave number measurement circuit 15 willcount the total value obtained when the value counted the wave number ofthe reference clock during the counting period from the time t0 to thetime tM is added to the value counted the wave number of the referenceclock during the period from the time t1 to the time tM+1. In short, thecounted result will be the same as the result obtained in the firstembodiment shown in FIG. 2.

FIG. 8 shows a configuration of a weight assigning wave numbermeasurement circuit. The weight assigning wave number measurementcircuit 15 shown in FIG. 8 has an adder 100, a count register 102 tohold the output of the adder, as synchronizing with the reference clockCb, and a weight assigning amount generator circuit 104 to supply theweight assigning amount S104 to one of the input of the adder 100. Theoutput OUT of the count register 102 is supplied to the other input ofthe adder 100. The weight assigning amount generator circuit 104generates the weight-assigning amount S104, in accordance with the wavenumber measurement result signal S16 to be supplied. As described inFIG. 7, for the amount of weighting, for instance, the minimum value of1 is set for the amount at the time when the counting period starts, andafter that time, 2 set for the amount while the wave number measurementresult S16 is between 2 through M, so that at the last cycle of thecounting period, the value becomes the minimum value of 1. Or, theamount of weighting can be set, so that the values become 1, 2, 3, 3 . .. 3, 2 and 1. In this case, the same result can be obtained, as when K=3in FIG. 1.

The weight assigning wave number measurement circuit shown in FIG. 8synchronizes with the reference clock Cb, and the adder 100 adds theamount of weighting S104 to the counted value registered in the countregister 102. The added value is held in the count register 102.

As shown in FIG. 7, in the second embodiment, even if the rising edge ofthe input signal agrees with the rising edge of the reference clock atthe time t0, or tM, counting failure can take place at the time t0 andcounting error becomes −1, and also, at the time tM, the amount ofweighting becomes 2 or 1, and the counting error can become +1, so, theresultant counted value becomes whichever one of 2N, 2N−1, or 2N+1.Therefore, the error accuracy is the same as given in the aboveexpression (6).

Now, the description is already made that in the first embodiment, byemploying of the quotient obtained when the minimum common multiple ofthe cycles of the input signal and the reference clock are divided bythe cycle of the input signal as the quantity of frequency measurementunits, error can be minimized. In the second embodiment, by changing theamount of weighting, the quantity of the frequency measurement unitsshown in FIG. 1 can be substantially changed. For instance, according toan external setting signal S105, the amount of weighting is set as

1, 2, 2 . . . 2, 1:  (1)

1, 2, 3, 3 . . . 3, 2, 1; or  (2)

1, 2, 3 . . . L, L . . . L . . . 3, 2, 1  (3)

and, the same measurement result can be obtained as in the case wherethe quantity of K=2, K=3, or K=L of frequency measurement units areprovided. Therefore, if the amount of weighting can be set externally, ageneral-purpose frequency measurement circuit can be embodied.

Therefore, for the cycle tm of the input signal and the cycle tB of thereference clock, the amount of weighting for obtaining the maximumaccuracy must include types at least equivalent to the quotient obtainedwhen the lowest common multiple of tm and tB are divided by tm. Inshort, it is satisfactory to set the value of the L given above to thequotient obtained when the lowest common multiple of tm and tB aredivided by tm.

The amount of weighting described above is not necessarily a positivenumber. It may be a negative number, and in this case, its absolutenumber becomes the minimum value at the time when counting starts and atthe time when counting ends, and only requirement is that the amount ofweighting gradually increases or decreases.

FIG. 9 shows a configuration of a filter characteristic adjustmentcircuit, an application example of the frequency measurement circuit.FIG. 10 is an operating waveform diagram of the adjustment circuit. Inthis example, the characteristic frequency of a filter device 110 madeby a semiconductor integrated circuit is measured, and adjustment of thefrequency is made possible. In FIG. 10, the control device 115 generatesa characteristic frequency control signal S115A, a selector controlsignal S115B, a step control signal S115C, and a measurement controlsignal S115D. In the adjustment process, a step signal generator device112 generates the step signal S112 shown in FIG. 10, and supplies thegenerated step signal. S112 to a filter device 110 through a selectorcircuit 113. The step signal S112 includes a signal of a wide frequencyband. Therefore, a signal having the frequency corresponding to thecharacteristic frequency of the filter device 110 will be outputted asthe output signal out of the filter device. If the filter device is aband-pass filter, the characteristic frequency is the center frequencyof its pass-through band. The response waveform out, which passedthrough the filter device 110 is, as shown in FIG. 10, a signal, whichdecays in a short period of time.

A response waveform cycle measurement device 114 corresponds to thefrequency measurement device in this embodiment. The response waveformfrequency measurement device 114 has a comparator function to comparethe response waveform out and the measurement reference level Vref andto generate the pulse signal PULS shown in FIG. 10. This pulse signalPULS is supplied as the input signal of the frequency measurement devicein this embodiment. And, by counting of the reference clock in a shortperiod of time, the frequency (cycle) of this pulse signal will bemeasured.

The response waveform cycle measurement device 114 gives the measurementresult S114 to a control device 115, and the control device 115 suppliesa characteristic frequency control signal S115A to the filter device110, depending on the measurement result, to adjust the characteristicfrequency. When the adjustment finished, dispersion of the process ordispersion of the characteristic frequency associated with the operatingenvironment will be removed. After the removal, a selector device 113switches to the input signal side, and supplies the received signal INof a cellular phone, etc. to the filter device 110 to obtain the outputsignal out of the filter device 110. The above application example isnothing but an example.

In accordance with the above embodiments, this embodiment will besummarized as follows.

The protective scope of the present invention is not limited to theembodiments described above, but the coverage extends to the inventiondefined in claims and to its equivalents.

Industrial Applicability

As described above, the present invention enables the frequencymeasurement device to minimize the measurement error (to improve theaccuracy in measurement) without the need to extend the measurementtime. Moreover, the present invention enables the frequency measurementdevice to improve the accuracy in measuring frequency, without the needto raise the frequency of the reference clock.

What is claimed is:
 1. A frequency measurement circuit for measuring afrequency of an input signal, comprising: a first frequency measurementunit for counting a reference clock during a first counting periodhaving a predetermined number of waves of the input signal; a secondfrequency measurement unit for counting the reference clock during asecond counting period having a predetermined number of waves of theinput signal; and an adder for adding the counted numbers of the firstand the second frequency measurement units, wherein the first and secondcounting periods shift overlap each other.
 2. The frequency measurementcircuit according to claim 1, wherein the first and the second frequencymeasurement units each include: a select signal generator circuit forcounting a predetermined number of waves of the input signal andgenerate a select signal during the counting period; a select circuitfor allowing a supply of the reference clock in response to the selectsignal; and a reference clock frequency measurement circuit for countingthe reference clock supplied from the select circuit.
 3. The frequencymeasurement circuit according to claim 1, wherein the number of thefrequency measurement units is at least equal to a quotient of thelowest common multiple of tm and tB divided by tm, where tm is the cycleof the input signal and tB is the cycle of the reference clock.
 4. Thefrequency measurement circuit according to claim 1 or 3, wherein theinput signal is a clock signal, and wherein the counting period startsfrom a rising edge or a falling edge of the input clock signal and endsat the rising edge or the falling edge of the input signal respectively.5. The frequency measurement circuit according to claim 4, wherein thepredetermined number of waves of the input signal is the number of therising edges, the number of the falling edges or the number of risingand falling edges of the input clock signal.